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4 layers board complete

ADC Schematic

ADC Full

ADC Top

ADC Ground

ADC Power

ADC Bottom

After quite a bit of hard work, we have a new board for the audio ADC converter, made of 4 layers: analog signals at the top, digital signals at the bottom, ground and power in the middle. No shared vias, no duplication of power inputs, no nasty capacitors on the audio input path. And thanks to this redesign, we managed to make the board a lot smaller: 86 × 38 mm.

Next step: audio DAC board.

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Single Bias Source

ADC

After careful consideration, I have decided to go for a single bias source, instead of two (left and right). The reference design for the AK5397 uses a single one, and I am worried that having two different voltage levels for left and right could create some unforeseen issues. This will make the PCB a bit less symmetrical than it would be with two levels, but better be safe than sorry.

Also, I have decided to get DVDDL and DVDDR (3.3 V) from AVDDL and AVDDR (5 V) respectively, instead of getting them from the +6V input, which should reduce the amount of power loss quite a bit. Finally, I have removed all capacitors from the audio input signals, as mentioned on this post.

I am now working on a 4 layer version of the PCB.

With a bit of luck, this should be the last major revision.

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Going for 4 layers

Following the advice of another mentor, I have decided to redesign my audio ADC module as a 4-layer board. This will give me the right impedance between power and ground, by putting them on two separate planes. The board will now be laid in the following fashion:

  • Top: Analog
  • Middle-Top: Power
  • Middle-Bottom: Ground
  • Bottom: Digital
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FPGA module received

I just received my FPGA module from Knowledge Resources. In fact, rather than receiving it in the mail, I flew to Basel to pick it up from Mike Stengle in person. He has put together an elite team of FPGA experts who can help me tackle some of the challenges that I am facing, not just for the ISHIZENO i8, but for the real project that is motivating all this research: building a machine for STOIC.

More on this later…

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Film capacitors

On my previous design, I made a total newbie mistake: putting tantalum capacitors directly on signal paths. This was quickly caught by one of the experts who is advising me on the project, and I’ve decided to replace them with film capacitors. Unfortunately, the ones we need must have a 220 μF capacity, which is a lot for a film capacitor. As a result, their individual size is 28.0 × 42.5 ×  41.5 mm, which is too large for our small ADC modules. Therefore, we’ve decided to mount them on the backplane instead. We will most likely use EPCOS film capacitors. Updated design coming soon…

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Redesigning ADC power section

Following the advice of a couple of mentors, I have decided to redesign the power section of my ADC module. The LM78L15 and LM79L15 used to convert ±18 V into ±15 V are too noisy, and using a linear regulator to go from 15 V down to 5 V would waste two thirds of the input power, while generating significant amounts of heat, which would induce additional noise.

A better solution would be to feed something like ±18 V and 6 V to the board, then use better linear regulators to get ±15 V, and keep the ADM7150 for going from 6 V to 5 V. Also, it would be best to get the 3.3 V that we need for the digital part of the ADC converter from the converted 5 V level, instead of getting it from the 6 V input.

To get the ±18 V and 6 V inputs, one of my mentors suggested that we use a regulator with high switching frequency (2 MHz) to filter out any remaining switching noise. And multiple such regulators could be used with frequency lock with a phase shift between them, delivering very low EMI emissions, and a virtually ripple free power source. This part will be done on the backplane or PSU board.

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Soekris inspiration

Awesome news: we just received permission from Soren Soekris, designer of the amazing Soekris dam1021 R-2R sign magnitude DAM, to order one of his DAC modules in order to get some inspiration from it. This should save us a ton of trials and errors.

We also got warned that:

  • We might want to use 4 layers instead of just 2.
  • We need to work on our terminations.
  • Some of our capacitors are not so great.
  • Our 15 V power regulator is too noisy.
  • FPGA firmware development will be hard.

Thank you Soren, very kind of you!

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