Output stage topology

This application note from ESS provides a great outline for the output stage that we could use in our audio interface. It also confirms that the AD797 operational amplifier is better suited than the LME49710 found in some lower-end DAC circuits.


Clock socket

The Pulsar Clock used on the DAC part of our audio interface will be mounted on a DIP-14 socket, so that it can be upgraded easily. Now, we need to figure out the best way to drive it. Also, I’m not sure how the master clock’s signal should be dispatched to our 9 ES9018 digital-to-analog converters…


Op-amps on all lines

As far as I can tell, many digital-to-analog converters do not include operational amplifiers on output lines. If you want them, you need to use this mod. Keeping with our no-limits approach, I’ve decided to add them to all our input and output lines. On the output side, the AD797 seems to be the default option with the ES9018, but I’m wondering if an OPA627 or OPA637 could be more suited.

In our initial design, the operational amplifiers will be used by default. But in future revisions, we will allow them to be by-passed, most likely by using some relays. This will be especially useful when connecting microphones to the analog audio inputs.


XMOS architecture

Slowly but surely, I am starting to undertand how the XMOS multicore microcontroller could be put to good use in our architecture. Since we now have a totally balanced design with dedicated ADC and DAC converters for every audio input and output, it makes sense to pair them with dedicated microcontrollers. This would free up the Zynq from any audio interfacing work, while being able to control our 17 audio converters individually.

On the audio input side, both the XMOS device associated to any given stereo audio input and the Zynq MPSoC would be connected to the same ADC converter output. On the audio output side, the XMOS device and the Zynq would be connected to the same DAC converter input. This would give our mesh of 17 XMOS devices direct access to the raw digital audio inputs and outputs.

From there, the 17 XMOS devices (XLF210 most likely) would be connected to a larger XMOS device used as primary audio interface (XEF216 most likely). This interface would be implemented using this reference design, thereby providing the following features:

  • S/PDIF optical/coaxial input
  • S/PDIF optical/coaxial output
  • ADAT input and output
  • MIDI input and output
  • USB Audio Class 2.0
  • Gigabit Ethernet with AVB
  • Lightning

The XMOS devices would be connected to the Zynq in a couple of ways: first, we would use their JTAG interfaces in a daisy-chained fashion for programming; second, we would use dedicated I/Os on the XMOS and Zynq sides for exchanging digital audio signals between the two. In a perfect world, this would be achieved by implementing the xCONNECT protocol on the FPGA side. Bad news: this is far from trivial. Good news: we do not need it initially.

Last but not least, we would use a similar architecture for CV inputs and outputs, using one XMOS device for CV inputs, and another one for CV ouputs. These would be connected to the ADC converters (AD7606), DAC converter (AD5360) and Zynq MPSoC in a fashion similar to the one described above.

Learn more about the full project on its website.


ATmega328 over SPI

After further consideration, I have decided to keep the ATmega328 microcontrollers for bargraphs, keypad, and portplate. But instead of connecting them over USB, I will use the Zynq’s SPI interface. This is made possible by the fact that we do not need a lot of bandwidth between the Zynq and these boards, nor a very low latency. As a result, it will remove the need for USB interfaces on the MCU side, and USB hubs on the MPSoC side. The SPI interface will be used both for programming the MCU (In System Programming) and for full duplex communication, using the Zynq as master.


Regulator Diagram

Screen Shot 2015-04-27 at 2.49.02 PM

Here is what our power regulator boards will look like. We will be using the ADM7150, but the input, output, and intermediate VREG lines will use a trio of capacitors mounted in parallel, instead of a single capacitor. Each line will have a 100μF tantalum capacitor, a 10μF XR7, and a 100nF C0G. This should help achieve the best possible results. Also, the two capacitors connected to the bypass line will be adjusted in order to tune the system. During the development phase, this tuning will be achieved by using some additional jumpers that will be removed on the final boards in order to make them as small as possible.

I’m really, really happy to have this part figured out…