System 0.1.6

Even when in (limited) production, the ISHIZENO i8 will remain an experimental device, and one of the areas of exploration that I am fascinated about the most is FPGA development. For this reason, I have decided to add 16 SMA connectors on the back planel in order to give direct access to the 16 GTH transceivers offered by the amazing Zynq UltraScale+ MPSoC that we will use eventually.

In case you’re not entirely familiar with these transceivers, they’re capable of providing 16.3 Gb/s of bandwidth on a single I/O, which means a total of 260.8 Gb/s in and out of the MPSoC. Having these connectors would allow us to connect multiple ISHIZENO i8 devices together in order to provide more audio inputs and outputs, and a lot more signal processing power, without any meaningful increase of jitter or latency. Another benefit would be to experiment with massively parallel processing between multiple MPSoC devices, because the ultimate goal of this little project of mine is to build a machine for STOIC. Excel formulas on FPGA! Yeah!


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