If you take a look at our pin assignment sheet and the block diagram above, you will see that we managed to nicely distribute load across all four Parallella boards, in a way that should simplify software development and improve performance. To do so, several elements were taken into consideration.
First, we assumed that the most critical element to distribute was the set of digital audio signals, for both inputs and outputs. Therefore, each Parallella board got its own stereo input and its own stereo output. On top of that, we assigned the mixed stereo output to submodule 4, simply because it is the closest to the audio ADC board, and because it is on the right side of the device, while considering that sound should flow from left to right.
From there, we decided that submodule 1 would be used to drive all controllers and most of the indicators. This will ensure that any user interaction is instantly reflected on the faceplate’s indicators, without requiring any communication between submodules. As a result, 44 out of 48 GPIO pins have been assigned on submodule 1.
After that, we decided to use submodule 2 for processing our 16 CV inputs, and submodule 2 for processing the 16 CV outputs and the 32 LEDs mounted on the portplate. This will require that submodule 2 sends CV input information to submodule 3, but this information should be limited, since it will be used only for the purpose of driving LED indicators. Furthermore, it is quite likely that many CV outputs will be derived from CV outputs, therefore submodule 3 will need access to CV inputs anyway. Having them side by side will therefore reduce the load on the Parallella mesh network.
Finally, we decided to use submodule 4 for driving the 9 motorized faders and their related dual bargraphs. This is due to the fact that submodule 4 will be used for mixing our 8 stereo outputs in the digital domain, therefore, it will need direct access to all audio outputs by definition. And we are using the same submodule for driving our mixed stereo output, for obvious reasons.
All that being said, there is no denying that what we have in front of us is a really complex architecture, with massive over-engineering. Everything about it is overkill, in many ways. But this is largely by design. The purpose of the exercise is not to develop a realistic device that could be met with market success. Instead, the intent is to make a statement, to create some kind of reference platform that can be used to learn a ton of things.
And learning we are…