One of the main benefits of using the Parallella board as submodule is the availability of a very fast mesh network for propagating digital audio and CV signals across submodules with very low latency and very high bandwidth. In that respect, the numbers are staggering:
- 512 GB/s local memory bandwidth
- 64 GB/s Network-On-Chip bisection bandwidth
- 8 GB/s off-chip bandwidth
- 1.5 ns network per-hop latency
With four submodules on board, we could use a simple and efficient square topology to connect them, leading to a low 3 ns maximum latency between submodules (2× 1.5 ns). Now, let’s take a look at what 8 GB/s off-chip bandwidth really means for us.
According to our current design, we have 16 audio inputs, 16 audio outputs, 16 CV inputs, and 16 CV outputs. Assuming that we could sample audio inputs on 32-bit at a rate of 384 kHz, we would need 1.536 MB/s of bandwidth per audio input. And if we assume that audio outputs would be sampled in the same fashion, we would need 49.152 MB/s for audio signals. Now, if we assume that all 4 submodules somehow need access to all audio signals (unlikely), we would need four times as much bandwith, or 196.608 MB/s.
From there, let’s take a look at CV signals. For CV inputs, the two AD7606 analog-to-digital converters will give us 200 kSPS for each channel, on 16 bit. That translates into 6.4 MB/s for our 16 CV inputs. On the output front, we could drive the AD5360 at 50 MHz, but that would be massively overkill. In such a context, we’re much better off assuming that we will use the same amount of bandwidth for CV outputs as we will for CV inputs. That translates into a total of 12.8 MB/s. And we can also assume that all 4 submodules will somehow need access to all CV signals. This would result in a total of 51.2 MB/s for CV signals.
Put together, audio signals and CV signals would require a bit less than 250 MB/s, which is 40 times less than the 8 GB/s off-chip bandwith offered by the Parallella board. In other words, we won’t have any problems moving our signals around through the mesh network of the Parallella architecture.
That being said, this mesh network is enabled by the E16G301 Epiphany microprocessor, but the Linux operating system running on every module will be hosted by another chip on the submodule, namely the Xilinx Zynq-7020. Therefore, the control of our converters, knobs, faders, buttons, bargraphs, and LEDs should be driven by the Xilinx. While the Xilinx could use the Parallella mesh network to communicate with each other, using a separate Gigabit Ethernet network would certainly be a lot easier, and we will need it anyway for connecting our system to the outside world.
In such a context, we’re thinking about embedding the printed circuit board of a MOTU AVB Switch within our enclosure. This would give us 5 AVB ports, one for each of the 4 submodules, and one for external connectivity (using the bakplate’s RJ45 port). It’s unclear that the Gigabit Ethernet port of the Parallella board could support the AVB protocol, but we could certainly add support for it later on by using 4 GPIO pins on the Xilinx Zynq-7020 and this piece of Xilinx IP.
With such a hybrid network architecture, we would use the internal Gigabit Ethernet network to pass control orders across submodules, while the Parallella mesh network would be used by audio and CV signals. And we would use the AVB element of the Gigabit Ethernet network to exchange audio signals with external systems like a digital audio workstation (DAW).